A fly-by transaction is defined as a transaction that results in the transfer of data directly between two devices coupled to a system bus, without storing the data in an intermediate buffer. Fly-by transactions are typically performed under the control of a direct memory access (DMA) controller. For example, a fly-by read operation may involve reading a data word from a slave peripheral device, transmitting the data word on a system bus, receiving the data word with a memory control unit, and the writing the data word to a main memory device. However, alignment issues may exist during the fly-by transaction. Alignment issues are generally described below in connection with FIG. 1.
FIG. 1 is a block diagram of a memory system 1 that includes a first memory device 10, a system bus 20, an aligner 30 and a second memory device 40. The first memory device 10 includes multiple rows. Each row entry has four byte locations “00”, “01”, “10”, and “11”. Alignment in the first memory device 10 is defined with respect to byte location “00”.
A first data word having four bytes “ABCD” and a second data word having four bytes “EFGH” are stored in the first memory device 10. The four bytes “ABCD” of the first data word are stored in byte locations “00”, “01”, “10” and “11”, respectively, in the first row of first memory device 10. The four bytes “ABCD” of the data word are therefore aligned with the byte location “00” in the first memory device 10. In contrast, the four bytes “EFGH” of the second data word are stored in byte locations “10”, “11”, “00”, and “01”, respectively, in second and third rows of the first memory device 10. The four bytes “EFGH” of the second data word are therefore not aligned with byte location “00” in the first memory device 10.
Data words are read out of the first memory device 10 onto system bus 20. System bus 20 includes four byte lanes for routing a data word, wherein each byte lane routes one byte of the data word. These byte lanes are labeled “00”, “01”, “10”, and “11” to correspond with the byte locations of the first memory device 10. Alignment of a word on system bus 20 is defined with respect to byte lane “00”. Thus, data word “ABCD” is aligned with system bus 20, while data word “EFGH” is not aligned with system bus 20.
Aligner 30 is coupled to receive the data word provided on system bus 20. Aligner 30 aligns the data received on system bus 30 with one of the byte locations “00”, “01”, “10” and “11” in the second memory device 40. As illustrated in FIG. 1, aligner 30 aligns the data word “ABCD” with byte location “01” of the second memory device 40. Similarly, aligner 30 aligns the data word “EFGH” with byte location “11” of the second memory device 40. While aligner 30 is capable of aligning data to any byte location in the second memory device 40, the transmitted data may not be aligned with respect to system bus 20. Other systems have suggested the use of aligners at two ends of a bus to ensure that data on the bus is aligned. However, these systems are not optimized for fly-by read and fly-by write operations. Other systems have attempted to solve the alignment problems on system bus by transferring data on a byte-by-byte basis, or by placing other constraints on the transfer of data (i.e., the number of bytes transferred must be a multiple of four and data buffers must be word aligned). Thus, these systems have many limitations. Accordingly, it would be desirable to have a system that overcomes the deficiencies of the prior art.